Embedded System on Chip Lab.
지도교수
이정근
- 학위 : 한림대학교 학사, 광주과학기술원 석사/박사
- 경력 : Univ. of Cambridge 연구원, UCLA 방문연구원, 광주과학기술원 연구교수
- 교육분야 : 논리설계/컴퓨터구조/임베디드HW
- 연구분야 : VLSI/SoC, 멀티코어프로세서
- 이메일 : jeonggun.lee@hallym.ac.kr
- 연구실 : 성호관 1306호
- 실험실 : 성호관 1201호
멀티코어프로세서설계
Introduction ↦ Motivation
-
"Multi-Core" Architecture?
- A multi-core CPU (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single integrated circuit(IC) called a die, or more dies packaged together
- Wikipedia
- A multi-core CPU (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single integrated circuit(IC) called a die, or more dies packaged together
-
Why do we need it?
- Moore's gab / Diminishing return
- Low power / Reliability
- Why Multi-Core? - Diminishing return
Our Missions
-
Core partitioning of a multi-core under workload & resource constraints
- Provide a simple performance, energy & process-variation model for multi-core Design Space Exploration
- Suggest insights on optimal core size and number of cores
Impacts of combining width other low power design techniques
-
In this talk,
- Develop asymptotic analysis models of Performance / Energy / Process-Variation-Aware Multi-core architectures with resource-constraints(i.e. constant die area)
- Optimize multi-core configurations based on the models
Core Partitioning for performance
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Speedup of resource-constrained multi-cores
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Optimum "core size" and "# of cores"
Decision Equation for Multicore
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When the condition "#COpt > 2" is satisfied?
- The case where the multi-core cna be a preferred solution
연구 내용
- 멀티코어 프로세서 분석 및 설계
- 비동기 회로 설계
- FPGA를 이용한 회로 고속화
- VLSI/CAD 개발
공동 연구
한국전자통신연구원
최근 연구 논문
- "Exploration of Power-Delay Tradeoffs with Heterogeneous Adders by Integer Linear Programming," In Jounal of Circuits, Systems, and Computers, Vol 18, No. 4PP.787-800, June 2009.
- "A Performance/Energy Analysis and Optimization of Multi-Core Archiectures with Voltage Scaling Techniques," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E93-A, No.6, pp.1215-1225, June 2010.
- "472 MHz Throughput Asynchronous FIFO Design On a Virtex-5 FPGA Device," IEICE ELEX, May 2011.